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In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.


Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0 and FF1 are HIGH. The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate.

FF2	FF1	FF0
0	0	0
0	0	1
0	1	0
0	1	1
1	0	0
1	0	1
1	1	0
1	1	1

The count sequence for the 3-bit counter is shown on the right. The most important advantage of synchronous counters is that there is no cumulative time delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency for this counter will be significantly higher than for the corresponding ripple counter.

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In a 2-way set associative cache, if one data word is empty for a read operation corresponding to a particular index, then it is filled. If both data words are filled, then one must be overwritten by the new data. Similarly, in an n-way set associative cache, if all n data and tag fields in a set are filled, then one value in the set must be overwritten, or replaced, in the cache by the new tag and data values. Note that an entire line must be replaced each time. The most common replacement algorithms are:

• Random -- the location for the value to be replaced is chosen at random from all n of the cache locations at that index position. In a 2-way set associative cache, this can be accomplished with a single modulo 2 random variable obtained, say, from an internal clock.
• First in, first out (FIFO) -- here the first value stored in the cache, at each index position, is the value to be replaced. For a 2-way set associative cache, this replacement strategy can be implemented by setting a pointer to the previously loaded word each time a new word is stored in the cache; this pointer need only be a single bit. (For set sizes > 2, this algorithm can be implemented with a counter value stored for each ``line'', or index in the cache, and the cache can be filled in a ``round robin'' fashion).
• Least recently used (LRU) -- here the value which was actually used least recently is replaced. In general, it is more likely that the most recently used value will be the one required in the near future. For a 2-way set associative cache, this is readily implemented by setting a special bit called the ``USED'' bit for the other word when a value is accessed while the corresponding bit for the word which was accessed is reset. The value to be replaced is then the value with the USED bit set. This replacement strategy can be implemented by adding a single USED bit to each cache location. The LRU strategy operates by setting a bit in the other word when a value is stored and resetting the corresponding bit for the new word. For an n-way set associative cache, this strategy can be implemented by storing a modulo n counter with each data word. (It is an interesting exercise to determine exactly what must be done in this case. The required circuitry may become somewhat complex, for large n.)

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A head access mechanism of the magnetic disk memory device for memorizing information by means of a rigid or flexible magnetic disk. The head access mechanism is equipped with a moving-coil type linear motor comprising an E-shaped yokes with two magnetic gaps and a movable coil. The yokes are arranged so as to produce the two magnetic gaps side by side on the extension itself of the plane of placement of the magnetic disk and/or plane parallel to it, with their openings opposing the magnetic disk. Magnets are installed on each of the magnetic gaps to align the magnetic flux toward the central yoke of the yokes. A movable coil is wound through the two magnetic gaps encircling repeatedly around the central yoke on which an indentation is provided, which extends parallel to the magnetic gaps. A carriage, which is housed mobile in side indentation and joined to said movable coil, supports the magnetic heads so as to restrain the magnetic coil, heads to be placed between the two magnetic loops that are formed by the pairs of magnets and the yokes.

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Direct memory access (DMA) is a feature of modern computers and microprocessors that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, sound cards and GPUs. DMA is also used for intra-chip data transfer in multi-core processors, especially in multiprocessor system-on-chips, where its processing element is equipped with a local memory (often called scratchpad memory) and DMA is used for transferring data between the local memory and the main memory. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Similarly a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time and allowing computation and data transfer concurrency. Without DMA, using programmed input/output (PIO) mode for communication with peripheral devices, or load/store instructions in the case of multicore chips, the CPU is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With DMA, the CPU would initiate the transfer, do other operations while the transfer is in progress, and receive an interrupt from the DMA controller once the operation has been done. This is especially useful in real-time computing applications where not stalling behind concurrent operations is critical. Another and related application area is various forms of stream processing where it is essential to have data processing and transfer in parallel, in order to achieve sufficient throughput.

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Programmed input/output (PIO) is a method of transferring data between the CPU and a peripheral such as a network adapter or an ATA storage device. In general, programmed I/O happens when software running on the CPU uses instructions that access I/O address space to perform data transfers to or from an I/O device. This is contrast to Direct Memory Access (DMA) transfers. Examples:

1. iF HoursWorked > NormalMax THEN
   Display overtime message
   ELSE
   Display regular time message
   ENDIF
2. 2. SET total to zero
   REPEAT
   READ Temperature
   IF Temperature > Freezing THEN
   INCREMENT total
   END IF
   UNTIL Temperature < zero
   Print total.